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Modeling and Simulation of Gated Memristor
N. Amarnath,
Published in Elsevier Ltd
Volume: 24
Pages: 1777 - 1787
Memristor's electrical behavior can be defined as inter-relationship between electric charge and magnetic flux. Memristor exhibit memory characteristics. Its present state resistance depends on the amount of charge passed through it in particular direction previously. This varying resistance property can be used as non-volatile memory property. Memristor have very steep off to on transitions with a large on-off resistance ratio. A device with more control terminal offer superior control over its characteristics than two-terminal devices. The unique characteristics of memristor along with long retention time and low complex device geometry make them ideal to model them as three-terminal devices. The prime objective of this paper is to model a drift based three terminal memristive (Gated Memristor) device that possess same memory, current characteristics and pinched hysteresis effect that of a two-terminal device. Further, the modeled device can be used to realize various novel digital and analog circuits. Device is modeled using Verilog-A language and simulated using Cadence Virtuoso environment. © 2019 Elsevier Ltd.
About the journal
JournalData powered by TypesetMaterials Today: Proceedings
PublisherData powered by TypesetElsevier Ltd