The constant delay (CD) logic makes high speed operation of the dynamic circuits possible. In the CD logic, the timing block plays a vital role as it helps in reduction of the evaluation time, by defining a small window width. This paper proposes a modified timing block which yields minimized area even while accomplishing the function. Use of the CD logic across cascaded stages employing the proposed timing block realises a larger area reduction and hence reduction in power dissipation. All the simulations are done using UMC 90nm technology node library at 1GHz frequency. © 2015 IEEE.