Memristor-based memories are one of the attractive candidates to replace present memory technologies due to its novel characteristics such as non-volatile storage, nanosize cell, compatibility with CMOS, low power dissipation, and multi-level cell (MLC) operation etc. However, the device needs to overcome the potential challenges such as process variations, non-deterministic nature of the operation, sneak path issues, non-destructive write and read operation. One of the most important characteristics of memristor memories is its ability to store multiple bits in one cell. In this paper, we design a low power, high-speed multi-level memristor based memories. Additionally, the performance analysis of the multi-level memristor memories has been performed under various memristor models and window functions. © BEIESP.