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Multi-level memristor memory: Design and performance analysis
G. Pooja, S. Murali Krishna,
Published in Blue Eyes Intelligence Engineering and Sciences Publication
Volume: 8
Issue: 4
Pages: 723 - 729
Memristor-based memories are one of the attractive candidates to replace present memory technologies due to its novel characteristics such as non-volatile storage, nanosize cell, compatibility with CMOS, low power dissipation, and multi-level cell (MLC) operation etc. However, the device needs to overcome the potential challenges such as process variations, non-deterministic nature of the operation, sneak path issues, non-destructive write and read operation. One of the most important characteristics of memristor memories is its ability to store multiple bits in one cell. In this paper, we design a low power, high-speed multi-level memristor based memories. Additionally, the performance analysis of the multi-level memristor memories has been performed under various memristor models and window functions. © BEIESP.
About the journal
JournalInternational Journal of Innovative Technology and Exploring Engineering
PublisherBlue Eyes Intelligence Engineering and Sciences Publication