Time sensitive networking becomes increasingly important in handling control and management information. Utilization of the existing infrastructure is considered to be an important issue due to the increasing demand. Since control/management data packets can use the existing infrastructure, this work study the basic requirements behind the Time Sensitive Network and ingress policies in it. Further proposes, the multilevel scheduling mechanism to support various class of service of Ethernet. © 2017 IEEE.

Umadevi K S

Department of Information Security

School of Computer Science and Engineering

Vellore Campus

R. K. Sridharan

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques

An Extension of the OMNeT++ INET Framework for Simulating Real-time Ethernet with High Accuracy

Proceedings of the IEEE

Evolution of the internet QoS and support for soft real-time applications

Multilevel ingress scheduling policy for Time Sensitive Networks

Journal	Data powered by Typeset2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
Publisher	Data powered by TypesetIEEE
Open Access	0