Background/Objectives: Domino Logic is extensively used in high performance microprocessor designs. The conventional pipelining of domino logic designs are more prone to timing overhead due to the factors, namely, clock skew, delay caused by the latches, and its inability to borrow time. Methods/Statistical analysis: The cascaded pipelined domino stages utilizes two and four phase clocks for sequencing the operation. The pipelined stages are sensitive to clock edges, and are incapable of borrowing time. Hence, latches are included between the consecutive stages to facilitate the pipeline. Considering the required computation time of the circuit, the speed enhancement in a domino logic pipelined circuit could be achieved by reducing the precharge and evaluation period. Findings: In this paper, four phase self-timed clocking scheme is implemented on a pipelined domino logic ALU. In addition to the maximum computation time of an individual stage, the setup and hold time are also considered for defining the clock evaluation time in the four phase scheme. Furthermore, it is ensured that the precharge operation happens only after the previous output is passed on to the next stage. The analysis and comparison of the conventional pipelined domino circuit design, the skew tolerant self timed pipeline design of an inverter chain and the ALU, using two phase and four phase overlapping clocks are done using Cadence® Virtuoso Spectre employing 180nm technology library and analyzed in the ADE-L environment. Improvements/Applications: The skew tolerant self-timed design of the domino logic pipelined ALU demonstrates an increased speed of 60% and reduction in power of 30% as compared to the single phase pipelined ALU design. © 2017 IEEE.