Research of multilevel inverter (MLI) has always been a noteworthy inspiration to increasing number of levels with decreasing total harmonic distortion (THD). Various topologies of symmetric dc source and asymmetric dc source multilevel inverter have been developed. In this paper, a new asymmetric dc source hybrid multilevel inverter topology with minimized switch count is proposed. It is possible to extent any number of levels. Multicarrier pulse width modulation techniques are adopted for triggering the gate pulses. The operation of the proposed topology is explained with 15-level output voltage. In that, phase disposition (PD) technique has 8.03% of THD when compared to the carrier overlapping (CO) technique. The simulation results are carried out by using MATLAB/Simulink with different modulation index. © 2015 IEEE.

Palanisamy K

Department of Energy and Power Electronics

School of Electrical Engineering

Vellore Campus

Prabaharan N

Fathima A.H

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

New hybrid multilevel inverter topology with reduced switch count using carrier based pulse width modulation technique

2015 IEEE Conference on Energy Conversion (CENCON)

2019 Innovations in Power and Advanced Computing Technologies (i-PACT)

Structure of Boost DC and Multilevel Inverter with Reduced Switches for 7 level

Among the renewable energy applications, the most popular inverters are cascaded multilevel inverters. Irrespective of numerous benefits these inverters face reliability issues due to the presence of more circuit components in the design. This has been a critical challenge for researchers in designing inverters with enhanced reliability by reducing the total harmonic distortion (THD). This paper proposes a 31-level asymmetric cascaded multilevel inverter for renewable energy applications. The proposed topology produces waveforms consisting of the staircase with a high number of output levels with lesser components with low THD. The investigations on the feasibility and performance of MLI under steady-state, transient, and dynamic load disturbances. The results are validated from a 1.6kW system which provides the proposed inverter. © 2019 IEEE.

Fulltext

IEEE Access

Real-Time Implementation of a 31-Level Asymmetrical Cascaded Multilevel Inverter for Dynamic Loads

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.

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Symmetrical and asymmetrical cascaded multilevel inverter for photovoltaic system

This article introduces a new reduced switch multilevel inverter topology that operates in asymmetric state. The advantage of proposed multilevel inverter is utilizing the lower device count when compared to traditional configuration. This paper depicts a hybrid pulse width modulation which includes three different carriers and unipolar references. The three different carriers are saw-tooth, triangular, inverted unipolar sine which is arranged in phase disposition technique. The effectiveness of proposed hybrid pulse width modulation (HPWM) technique is tested with a new reduced switch topology using MATLAB/Simulink. The different parameters are calculated with various modulation indices. © Springer Nature Singapore Pte Ltd. 2018.

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Journal	Data powered by Typeset2015 IEEE Conference on Energy Conversion (CENCON)
Publisher	Data powered by TypesetIEEE
Open Access	No