The proposed project utilizes the computational speed advantages of Vedic algorithm and energy optimization benefits of Reversible circuit. The Vedic algorithm optimizes the conventional mathematic computation logic used in the current processors thereby, effectively increasing the speed of computation. The Urdhva Triyambakam method derived from the ancient Indian mathematics will be used in the proposed project. Reversible circuits, on the other hand, reduces the power dissipation incurred due information/bits loss as in the case of an irreversible circuit making way for better power utilization along with reduced heat dissipation. The proposed project introduces the concept of application specific reversibility wherein the logical states belonging only to a particular function of the module is being considered, which significantly impacts in reducing the area limitations of a reversible unit while keeping its power efficiency benefits. The circuit design presented utilizes the above technique mentioned while designing the adder, multiplier along with other modules of an ALU. © 2015 IEEE.