In this work we evaluated arrival profile of the HPM based multiplier partial products reduction tree in two ways: 1.manual delay, area calculation through logical effort, 2.ASIC implementation. Based on the arrival profile, we worked with some recently proposed optimal adders and finally we proposed an optimal hybrid adder for the final addition in HPM based parallel multiplier. This work derives some mathematical expressions to find the size of different regions in the partial product arrival profile which helps to design optimal adder for each region. This work evaluates the performance of proposed hybrid adder in terms of area, power and delay using 90nm technology. This work deals with manual calculation for 8-b and ASIC simulation of different adder designs for 8-b, 16-b, 32-b and 64-b multiplier bit sizes. © 2012 IEEE.

Ramkumar T

Department of Computer Applications

School of Information Technology and Engineering

Vellore Campus

Kittur Harish Mallikarjun

Department of Micro and Nanoelectronics

School of Electronics Engineering

Dandu V.B

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Optimization of hybrid final adder for the high performance multiplier

2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. © 2010 IEEE.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low-Power and Area-Efficient Carry Select Adder

2009 International Conference on Advances in Recent Technologies in Communication and Computing

Performance Analysis of Fast Adders Using VHDL

IEEE Transactions on Computers

High-speed Booth encoded parallel multiplier design

Journal of VLSI signal processing systems for signal, image and video technology

Design strategies for optimal hybrid final adders in a parallel multiplier

A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

Journal	Data powered by Typeset2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)
Publisher	Data powered by TypesetIEEE
Open Access	No