In this work we evaluated arrival profile of the HPM based multiplier partial products reduction tree in two ways: 1.manual delay, area calculation through logical effort, 2.ASIC implementation. Based on the arrival profile, we worked with some recently proposed optimal adders and finally we proposed an optimal hybrid adder for the final addition in HPM based parallel multiplier. This work derives some mathematical expressions to find the size of different regions in the partial product arrival profile which helps to design optimal adder for each region. This work evaluates the performance of proposed hybrid adder in terms of area, power and delay using 90nm technology. This work deals with manual calculation for 8-b and ASIC simulation of different adder designs for 8-b, 16-b, 32-b and 64-b multiplier bit sizes. © 2012 IEEE.