Novel area and energy efficient 2N-N-2P adiabatic logic with less leakage, switching noise and glitch free outputs is presented. FinFETs replace MOSFET for reduced short channel effects, lower leakage, less area and operating speeds. 2N-N-2P logic is validated using 32nm MOSFET and FinFET models and by comparison with 2N-2N2P and PFAL. FinFET circuits are compared with CMOS counterparts using benchmark inverters, Full adder, 512 inverter cascades and 4-bit CLA. The analyses also authenticate better performance under process parameter variations and demonstrate advantages of the use of FinFET for all the Evaluate, Hold and Recovery phases. © 2017 The Author(s).

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Bhuvana B.P

Fulltext

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VIT University

Procedia Computer Science

This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.

Journal of Circuits, Systems and Computers

Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures

In this article, a novel low power adiabatic circuit, namely the modified complementary pass transistor logic (MCPAL) powered by a four phase power clock supply, is proposed. The important features of the proposed logic are its low leakage power, glitch free output, and lower switching noise compared to the counterpart circuits found in the literature. Efficiency of the proposed adiabatic logic is validated by comparing with the basic inverter circuits designed using 2N2P, 2N-2N2P, PFAL, CPAL, and DCPAL type of adiabatic logic circuits. Secondly, the utilization of self-aligned double gate FinFETs in the design of MCPAL is also studied, with the use of an inverter and 512 stages of cascaded inverters implemented using 32 nm FinFET and 32 nm lower technology MOSFET by employing their corresponding BSIM model files. The circuits are designed and simulated in Cadence Virtuoso® tool environment through an operating frequency range from KHz to GHz. © Springer Nature Singapore Pte Ltd. 2018.

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

A Novel Adiabatic Logic for Low Power VLSI Circuit Design and Power Optimization Using FinFET

Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)

Design and Analysis of FinFET Based CSCPAL Low Power Adder

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs

India International Conference on Power Electronics 2010 (IICPE2010)

Energy recovery performance of quasi-adiabatic circuits using lower technology nodes

IEEE Electron Device Letters

Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

IEEE Transactions on Electron Devices

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

Journal	Data powered by TypesetProcedia Computer Science
Publisher	Data powered by TypesetElsevier BV
ISSN	1877-0509
Open Access	No