In this article, we focus on the extensively utilized algorithm for Fast Fourier Transform (FFT) radix-2 DecimationInTime (DIT). It proposes a variable-length FFT processor that can be reconfigured. The processor designed for different FFT / IFFT stages can perform 8, 16 and 32 point FFT / IFFT with different word length scaling modes. Furthermore, in many applications, the processor is suitable for various FFT / IFFT length requirements. Single-path delay feedback (SDF) pipeline architecture is incorporated in order to achieve higher throughput. Cadence NC Launch, RTL Compiler, Simvision Simulator and Altera DE2 FPGA EP2C35F672C6 board are used to test the design in TSMC 45 nm technology. We often worked with 2/3/5 radices and thus make a clear comparison between different radices and the efficiency associated with each of them. This work achieves better specifications for area use and delay. Meanwhile, the occupied resources are approximately same. Moreover, the performance of different FFT length is analyzed. © 2020 IEEE.