Multiplication is one of the main functions in a Digital Signal Processing System. The vedic multiplier operation will have an impact on the efficiency of the system. This leads to the development of high speed adder and multiplier. In this paper, the architecture is proposed to perform high speed multiplication using ancient Vedic mathematics. O ne of the most efficient sutra in Vedic mathematics named as Urdhva Tiryakbhyam. The Urdhva multiplier generates the partial products and the sums in parallel. Hence, this multiplier reduces the carry propagation delay from LSB to MSB. To achieve better performance characteristics a high speed CSKA is needed. The improvement in the characteristics of efficiency is obtained by considering the high speed CSKA. In addition, the proposed structure makes use of AOI and OAI compound gates for the skip logic exha usting the conventional logic. Hence due to the above all characterizations the proposed CSKA is preferred than the different types of adders for implementation. © 2018, Institute of Advanced Scientific Research, Inc.. All rights reserved.