Multipliers are the basic building blocks of signal processing and arithmetic based systems. The objective of this paper is to design a high speed multiplier that significantly improves the performance of many high performance DSP, multimedia and communications systems. This paper proposes a high speed radix 8 Booth multiplier employing signed digit representation for recoding and radix 8 modified Booth algorithm that reduces the number of partial products to n/3. The design of the multiplier is based on Wallace tree architecture with considerable improvement in performance. This paper compares the performance of conventional multiplier with radix 4 tree based Booth multiplier and radix 8 tree based Booth multiplier. The radix 8 tree based Booth multiplier is synthesized using Quartus II simulation tool. The proposed radix 8 tree based multiplier exhibits better performance with respect to area and operating frequency when compared to conventional multiplier.

Sivasubramanian A

Electronics

School of Electronics Engineering

Chennai Campus

Hemanandh S

Fulltext

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Indian Journal of Science and Technology

Design of Fused Add-Multiply Operator using Modified Booth Recoder for Fast Arithmetic Circuits

Background: Multiplication is the basic operation in any signal processing systems and financial applications, all these applications requires multiplication to be performed in a faster and efficient manner on a silicon chip. Methods: This paper describes the algorithm and architecture of a BCD parallel multiplier. The design exploits two properties of redundant BCD codes to speed up its computation. Namely, the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition to this, number of new techniques are used in order to reduce significantly latency, area and for implementation on FPGA compared to existing implementations. Findings: Parallel architecture is used for generating partial products using radix-10 recoding technique for signed-digit of a BCD multiplier having set of digits between the range [-5, 5] and a positive set of multiplicand multiples coded in XS-3. Use of this encoding has various advantages like, as XS-3 is a self-complementing code, finding a negative of it is by just complementing the bits of respective number. Also the redundancy in XS-3 code is utilized for generating multiplicand multiples in a simple, faster and a carry-free way. Implemented design has three stages. Partial product generation, reduction and final conversion to BCD. For to implement the design in hardware the partial product reduction architecture is modified here to use a bank of ripple carry adder trees. ODDS representation uses 4-bit binary encoding technique which is similar to non-redundant BCD code, for this reason conventional VLSI circuit techniques such as carry-save adders and compression trees can be used effectively to perform operations on decimal numbers. Conclusion: To show the advantages of the resulted design, RTL model for 8 × 8-digit and 16 × 16-digits multiplication has been synthesized and implemented in Virtex-5 FPGA device. Results shows that the multiplier is about 10-15% delay efficient with existing work and about 14-18% area efficient.

Implementation of Fast Radix-10 BCD Multiplier in FPGA

Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity

In many multimedia and digital signal processing systems, fixed-width multipliers are used where a fixed format is desirable and a tolerable level of loss in accuracy is permitted. This paper proposes the design of a low error fixed-width radix-8 Booth multiplier which produces an n-bit product with two n-bit inputs. The truncation of the 2n product bits to n bits is achieved by removing about half the adder cells that are required to add the partial products. However, in order to keep the truncation error to a minimum, error compensation biases are obtained and applied to the inputs of the retained adder cells. In this proposed technique, the number of partial products is reduced to n/3 and also the number of adder cells is reduced by 50% compared with the full-width multiplier with an additional overhead of one full adder for compensation biasing. Simulation results reveal that a significant amount of error reduction is achieved with this technique. Standard EDA design environment using 180nm technology has been employed. Validation has further been made in comparison against the modified Booth fixed-width multiplier architecture. © 2014 IEEE.

2014 Fifth International Conference on Signal and Image Processing

Design of a Low Error Fixed-Width Radix-8 Booth Multiplier

2014 First International Conference on Computational Systems and Communications (ICCSC)

Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications

Performance Evaluation of High Speed Radix 8 Tree Based Multiplier

Journal	Indian Journal of Science and Technology
Publisher	Indian Society for Education and Environment
ISSN	0974-6846
Open Access	No