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Performance Evaluation of Multi DC and Single DC Source on Cascaded Multi-Level Inverter
J. Gowrishankar, , E. Kaliappan, N. Prabakaran, G. Balasundaram
Published in Springer Science and Business Media Deutschland GmbH
Volume: 700
Pages: 211 - 220
In Cascaded Multi-Level Inverter (CMLI), the multi DC source and single DC source of asymmetrical and symmetrical Multi-level Inverters (MLI) are analyzed in this research paper. In single DC source, the switching pulse generation for nine-level H-bridge CMLI is generated using Phase Disposition Pulse Width Modulation (PDPWM). Here, four H-bridge CMLI has parallel connection, and the output of each H-bridge CMLI with the primary side of the transformer is also linked in parallel. The secondary side of the transformer is connected in series with load. It consists of one H-bridge inverter, 8 diodes, and two-bidirectional switches for bidirectional current flows through two switch S5, S6, and S7. The capacitor C4, C3, C2, and C1 are meant to separate the input DC voltage by Vdc, 3Vdc/4, Vdc/2, and Vdc/4. In multi DC source of symmetrical and asymmetrical CMLI switches are controlled by using Low-Frequency Pulse Width Modulation Technique (LFPWM). The nine-level symmetrical CMLI DC voltage source are Vdc1 = 1, Vdc2 = 1, Vdc3 = 1, and Vdc4 = 1. The 31-level asymmetrical CMLI DC voltage source are Vdc1 = 1, Vdc2 = 2, Vdc3 = 4, and Vdc4 = 8. All the multi DC Source and single-DC source of CMLI are analyzed in MATLAB software platforms. Comparison of the results with these simulations has been made, and the performance of the proposed system indicated by the THD. Hardware implementations have been done for asymmetrical MLI by using TMS320F2802A processor. © 2021, Springer Nature Singapore Pte Ltd.
About the journal
JournalData powered by TypesetLecture Notes in Electrical Engineering
PublisherData powered by TypesetSpringer Science and Business Media Deutschland GmbH