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Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs
Poorvasha S,
Published in IEEE
This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si1-xGex based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si1-xGex is optimized to get ON current (ION) enhancement. Si1-xGex based DG TFETs with gate-drain overlap offers a very good ION of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si1-xGex. © 2016 IEEE.
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JournalData powered by Typeset2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
PublisherData powered by TypesetIEEE
Open Access0