This paper studies the performance of asymmetric gate oxide on gate-drain overlap for Si and Si1-xGex based double gate (DG) Tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. For the different values of the mole fraction (x), Si1-xGex is optimized to get ON current (ION) enhancement. Si1-xGex based DG TFETs with gate-drain overlap offers a very good ION of 232 μA with the subthreshold swing (SS) of 26 mV/dec. This is achieved because of the high tunneling rate of electrons occurring at the source side of Si1-xGex. © 2016 IEEE.

Lakshmi B

Electronics

School of Electronics Engineering

Chennai Campus

Poorvasha S

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

&nbsp;

&nbsp;

VIT University

Performance of asymmetric gate oxide on gate-drain overlap in Si and Si 1−x Ge x double gate tunnel FETs

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

This paper deals with the effect of structural and doping parameter variations on RF parameters for Si and Si 1-xGe x-based double gate (DG) tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. The DC parameter subthreshold swing (SS) and RF parameter metrics, unity gain cut-off frequency (ft) and maximum oscillation frequency (fmax) are extracted by varying structural parameters, gate length (Lg), gate oxide thickness (tox), channel thickness (tch), doping parameters, channel doping (Nch), drain doping (Nd) and source doping (Ns) in and around their nominal value. For a channel thickness of 15 nm, a very less SS of 8 mV / dec is achieved in Si 1-xGe x-based DG TFETs with gate-drain overlap. Variations of gate oxide thickness offer better RF performance enhancement for Si-based asymmetric gate oxide devices. This could be achieved because of the higher tunnelling rate of electrons occurring at the source side of asymmetric gate oxide devices. © 2018, Indian Academy of Sciences.

Pramana

Influence of structural and doping parameter variations on Si and Si 1 - x Ge x double gate tunnel FETs: An analysis for RF performance enhancement

3D TCAD Simulation for CMOS Nanoeletronic Devices

Introduction of Synopsys Sentaurus TCAD Simulation

IEEE Journal of the Electron Devices Society

Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

Solid-State Electronics

Silicon–germanium nanowire tunnel-FETs with homo- and heterostructure tunnel junctions

Japanese Journal of Applied Physics

Tunneling field-effect transistor with Si/SiGe material for high current drivability

An analysis on the ambipolar current in Si double-gate tunnel FETs

Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

Journal	Data powered by Typeset2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
Publisher	Data powered by TypesetIEEE
Open Access	0