Harish Babu N

Satish Reddy N

Devendra B

Jayakrishanan P.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Pipelined architecture for vedic multiplier

2014 International Conference on Advances in Electrical Engineering (ICAEE)

Digital multipliers are indispensable in the hardware implementation of many important functions such as DCT, IDCT, FFT etc in signal processing. This paper deals with Design and implementation of Vedic Multipler in Image Compression using DCT algorithm. The DCT (Discrete Cosine Transform) performs spatial compression of the data while IDCT performs decompression of the data. Here, matrix multiplication is one of the important step in both the transforms. Hence, to perform these computations, we introduce Vedic multiplier which is based on Urdhava Tiryakbhyam(vertical and crosswise) sutra. In this paper, we have designed DCT algorithm using Verilog and code is written in Xilinx I.S.E 7.1i version, synthesized on Xilinx Synthesis Tool (XST). We retrieved Register Transfer Logic (RTL) and the simulation results are observed on Modelsim 6.0 Simulator. These simulation results were compared with matlab simulation results. From the comparison, we see that DCT using Vedic Multiplier is efficiently implemented and the proposed Vedic multiplier significantly improves the computational speed involved in multiplication operations of the image processing. Hence, Vedic multipliers can find immense use in applications of image processing to save time and area. © 2014 IEEE.

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

Implementation of vedic multiplier in image compression using DCT algorithm

International Journal of Recent Technology and Engineering Regular Issue

Design and Implementation of Vedic Multiplier

International Journal of Recent Trends in Engineering and Research

PIPELINED VEDIC MULTIPLIER

International Journal of Computer Applications

Design of 4x4 bit Vedic Multiplier using EDA Tool

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications

A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

Journal	Data powered by Typeset2014 International Conference on Advances in Electrical Engineering (ICAEE)
Publisher	Data powered by TypesetIEEE
Open Access	0