This paper proposes two-parallel pipelined fast Fourier transform (FFT) architectures for the discrete Fourier transform (DFT) computation of real-valued signals. The architectures are optimized with less number of registers for signal processing and wireless communication applications. The clock to registers is disabled to avoid storing of the redundant values and hence the registers actually storing those redundant values are eliminated. The proposed architectures requires 22% less registers than the prior architectures. The real-valued FFT (RFFT) processor is further optimized to process BPSK outputs in which case 43% of register is reduced. © 2014 IEEE.