A novel phase-locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage-controlled oscillator is proposed in this study. Composite PFD offers higher-gain and loop bandwidth (BW) during tracking when Δ ϕ > p and provides a lower-gain and loop BW during tracking when Δ ϕ < p as well as after lock-in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non-linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal-oxide-semiconductor process is found to achieve reference spur of -71.4 dBc, lock time of 2.05 μs, peak-to-peak jitter of 3.412 ps, phase noise of -110 dBc/Hz at 100 kHz and final placement area of 0.244mm2. © 2018, The Institution of Engineering and Technology.