In recent years, side channel attacks such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) are the most common in cryptographic hardware systems. Smart Cards, RFID tags, military communications and electronic commerce are some of the applications where cryptography plays a significant role. Adiabatic logic design is one among various low power VLSI design techniques used in the design of cryptographic hardware systems. In this paper, we propose the Positive Feedback Symmetric Adiabatic Logic (PFSAL) which reduces the energy dissipated by the S-Box circuit used in the cryptographic designs. Proposed PFSAL is validated by the design of the PFSAL based Rijndael S-Box. The efficiency of the proposed design is validated by comparing it with Rijndael S-Box designed using other existing security based adiabatic logic circuits. Results are simulated in Cadence Virtuoso. Proposed PFSAL is competent in terms of energy consumption, uniform power and current traces when compared with the existing counterparts. © 2018 IEEE.