Addition is a vital operation in all data paths. The power dissipation and speed performance remain the primary factors that identify the choice of adders. To achieve the desired energy efficiency or lower power dissipation, the selection of the particular adder topology plays a major role. The operating speed of adder or the circuit latency of adder can be minimized by the use of architectures such as Parallel Prefix Adders (PPAs). This paper presents a radix-4, 32-bit Parallel Prefix Adder with a sparseness of 4. The work involves the structural realization and implementation of a 32-bit adder using radix-4 and comparison with a radix-2 32-bit adder for the power, delay, power-delay-product (PDP) and the number of computational nodes. Simulation results reveal that the radix-4 32-bit Parallel Prefix Adder realizes minimum PDP. The effects of introducing the radix-4 and sparseness on power and delay parameters of the adder structure are analyzed. Cadence EDA tool is used for the schematic implementation of the adders and simulations have been performed using 180nm bulk CMOS technology. © 2014 IEEE.