in present semiconductor industry, designing the IP cores with shrinking in the silicon area is becoming challenging day by day, on top of it power and speed (timing) are the major challenges which decides the profit of the core. So to design IP cores with good quality in short period of time we can automate the design. RLS (RTL to Layout Synthesis) is Synopsys automation tool used for core design. Here timing, power, area and quality are the major challenges faced in design flow because any small issue can render the whole chip useless which may lead to heave economic loss. Hence it is imperative that the whole design of the functional unit which in total forms a core be as optimized as possible and meeting all the specs. But there will be tradeoff between power, area and timing. To achieve a good quality core various design techniques are applied in synthesis flow and in ECO mode also. Such that design timing get converged and power, area optimization can be achieved. In this project work major focus is on designing the repeater FuBs (Functional unit Blocks) and detail explanation on timing convergence, power optimization and achieving good quality on the design block. © 2018 IEEE.