The Content Addressable Memory (CAM) is a high throughput large capacity hardware device. It searches stored lookup data in parallel but consumes a large amount of power. NOR CAM cell offers high speed but suffers from high power consumption due to a short circuit current path in the precharge phase during mismatch. The Self-Controlled Precharge Free (SCPF) CAM cell, which removes the precharge phase offers low power consumption. As technology scales down, the reliability of memory nodes are sensitive to Soft Errors Single Event Upsets (SEUs). In this paper, a NOR CAM cell with different types of SRAM cells has been studied by inserting Double Exponential Current Pulse (DECP) at sensitive nodes of a memory cell for soft error hardened design. In addition, radiation hardened precharge-free CAM cell has been proposed for low power and high-performance design. The proposed CAM cell design and soft error hardened NOR CAM cell designs had been simulated and verified using Virtuoso tool at 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. Process corner simulations for search delay and power are performed on proposed and existing CAM cells. Simulation results show that proposed CAM cell exhibits 76.95% lesser energy than NOR-type CAM and 37.27% lesser energy than SCPF CAM cell design. © School of Engineering, Taylor’s University.