The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.