The multilevel inverters are in the focus in recent years. This is due to their advantages over the conventional three-level inverters. It is possible to obtain a nearly sinusoidal waveform using multilevel inverters. Due to this, the power quality is also improved. Also, they made possible to use the medium power switches in the high power applications. In this paper, new asymmetric 49-level cascaded multilevel is proposed by adding two 25-level multilevel inverters. The two inverters are operated at a delay with respect to each other, and the outputs of them are added in the load, thus obtaining a 49-level output. The main advantage of this inverter is that even if a switch is damaged the particular inverter module can be isolated and it can be operated in 25-level mode. This enables no much depletion in power quality and moreover, it assures the continuity of power supply. The viability and effectiveness of the proposed inverter is confirmed through simulation and experimental using laboratory experimental set-up.. © 2019 IEEE.

Dhanamjayulu C

Department of Control and Automation

School of Electrical Engineering

Vellore Campus

Arunkumar G

Department of Energy and Power Electronics

Elangovan Devaraj

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

&nbsp;

&nbsp;

VIT University

2019 Innovations in Power and Advanced Computing Technologies (i-PACT)

This paper implements and compares a symmetric hybridized cascaded multilevel inverter and an asymmetric multilevel inverter utilizing a switched capacitor unit for 17 level inverters. The symmetric hybridized multilevel inverter topology consists of a modified H-bridge inverter, which results in an increase in the output voltage to five level from the three level by using a bi-directional switch at the midpoint of a dual-input dc source. In the proposed asymmetric multilevel inverter, dc sources are replaced with the switched capacitor unit, which in turn boosts the output voltage and produces twice the voltage levels at the loads. The proposed topology with the staircase modulation technique has been verified using MATLAB-SIMULINK, and the results are experimentally executed with prototype models, which are interfaced with dSPACE RTI 1104. The results of the proposed topologies are experimentally obtained for steady state, and the performance of the same is tested under different resistive and inductive load disturbance conditions. The results substantiate that these multilevel inverter topologies are better stabilized during load disturbance conditions with low total harmonic distortion, a lesser number of switches, and increased output voltage levels, and these topologies well suit for renewable energy applications. © 2013 IEEE.

Fulltext

IEEE Access

Implementation and Comparison of Symmetric and Asymmetric Multilevel Inverters for Dynamic Loads

In recent past, numerous multilevel architectures came into existence. In this background, cascaded multilevel inverter (CMLI) is the promising structure. This type of multilevel inverters synthesizes a medium voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltage and current waveforms. However, when the number of levels increases switching components and the count of dc sources are also increased. This issue became a key motivation for the present paper. The present paper is devoted to investigate different types of CMLI which use less number of switching components and dc sources and finally proposed a new version of Multi-cell based CMLI. In order to verify the proposed topology, MATLAB – simulations and hardware verifications are carried out and results are presented. © 2016 Ain Shams University

Ain Shams Engineering Journal

Investigation on cascade multilevel inverter with symmetric, asymmetric, hybrid and multi-cell configurations

A boost dc-ac inverter is one which is capable of generating in a single stage ac voltage whose peak value can be higher or lower than the given input dc voltage. The major problem with this system is that the closed loop gain parameters kp and ki have to be optimized because these parameters help us to get desired result with better system response by lowering the rise time, settling time, peak overshoot and steady state error. Moreover when they are not optimized load line disturbances arise because of which the stability of output voltage decreases and THD value increases. So to overcome these difficulties bacterial foraging algorithm is being used. © 2016 The Authors.

Journal	Data powered by Typeset2019 Innovations in Power and Advanced Computing Technologies (i-PACT)
Publisher	Data powered by TypesetIEEE
Open Access	No