In this paper, 2D integer wavelet transform based watermarking is carried out for the grayscale image with its VLSI architectural implementations. In the 2D integer wavelet transformation the lifting scheme is adopted and the watermarking operation is carried out in the LL2 frequency subbands. The entire watermark embedding process and extraction process are modeled in MATLAB and analyzed against the signal processing attacks like compression, salt & pepper noise, rotation and Intensity transformation attacks. Finally the same algorithm is modeled using Verilog HDL and implemented using ALTERA QUARTUS-II. © 2016 IEEE.

Sakthivel S M

Electronics

School of Electronics Engineering

Chennai Campus

Ravi Sankar A

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Real time watermarking of grayscale images using integer DWT transform

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)

Digital image watermarking has become more popular due to its applications in copyright protection and secret communication. Most of the image watermarking algorithms reported till date involve modification of the host contents for embedding a secret data, leading to a reduced robustness and a limited embedding capacity. In the present work, a novel spatial domain watermarking scheme called Pixel Value Search Algorithm (PVSA) is proposed using a linear search operation to achieve high robustness and a theoretically unlimited embedding capacity. In the proposed scheme, secret data are embedded into a host image by mapping their intensity values into row and column locations. Due to this linear mapping of secret data, the host structural content is not altered. In addition, multiple watermarks can be mapped into a single host image using the PVSA technique. The proposed algorithm is verified using MATLAB® simulations and its performance characteristics are assessed using a standard benchmark tool called strimark. Experimental results illustrate the robustness of the PVSA technique against the attacks of Gaussian blurring, Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, mean and median filtering, histogram equalization, image sharpening, intensity transformation, unsharp filtering, JPEG attack, etc. Subsequently an ASIC implementation of the PVSA algorithm is carried out using Verilog HDL and various modules of the Cadence® EDA tool so as to integrate the chip as a watermark co-processor. The ASIC implementation using a 0.18 μm technology at an operating frequency of 100 MHz consumes a power of 326.34 μW for the complete hardware architecture. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.

Multimedia Tools and Applications

An ASIC based invisible watermarking of grayscale images using pixel value search algorithm (PVSA)

Computers & Electrical Engineering

Computation-efficient image watermarking architecture with improved performance

2017 25th European Signal Processing Conference (EUSIPCO)

Sessions: 2017 25th European Signal Processing Conference (EUSIPCO)

Journal of Multimedia

A Combined DWT and DCT Watermarking Scheme Optimized Using Genetic Algorithm

Digital watermarking is the technique used to embed author's credentials, logo or some other information into digital images which can be used in authentications for courtroom evidence, copyright claims and other applications. The objective of this work is to develop a feasible and invisible watermark embedding hardware for the secure digital cameras using LeGall 5/3 (Discrete Wavelet Transform) DWT. Bind watermarking tecnique is proposed here.The proposed architecture considers constraints of digital camera such as area, speed, power, robustness and invisibility. The algorithm is evaluated under the attacks like JPEG (Joint Photographic Experts Group) compression, noise, scaling and rotation to verify robustness and invisibility properties. Watermarking processor is described using Verilog HDL and synthesized using 0.18 μm technology UMC standard cell library for VLSI implementation. © 2010 IEEE.

Proceedings - 3rd International Conference on Emerging Trends in Engineering and Technology, ICETET 2010

VLSI architecture of DWT based watermark encoder for secure still digital camera design

2008 IEEE International Conference on Multimedia and Expo

Attack by colorization of a grey-level image hiding its color palette

IEEE Transactions on Circuits and Systems II: Express Briefs

A dual voltage-frequency VLSI chip for image watermarking in DCT domain

Journal	Data powered by Typeset2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
Publisher	Data powered by TypesetIEEE
Open Access	No