The RC5 Algorithm is a symmetric block based, cipher which has been chosen because of its features such as simplicity of operation, implementation and its parameterizable nature. This work tries to realize the RC5 cipher on an ASIC chip and on a FPGA. The design is optimized to improve latency, throughput, area and power constraints using techniques such as loop wrapping, pipelining, parallel processing and resource sharing. A hardware implementation of the cipher has the advantage of improved speed of operation compared to a software implementation and it also improves its security. The FPGA Implementation has been done on the DE1 board while reports were taken using Xilinx ISE. The design was made reconfigurable to accept two values of rounds and keys. The ASIC Implementation was done using a fixed choice of parameters. The results achieved for area, throughput and power for an ASIC Implementation is presented. The proposed solution could be used for security in a range of applications such as wireless sensor network nodes, network devices such as routers, servers and in mobile devices. © 2006-2015 Asian Research Publishing Network (ARPN).