The Residue Number System (RNS) performs parallel,carry-free arithmetic operations and has a shorter critical path with higher power efficiency. A RNS based Finite Impulse Response(FIR) filter is specifically designed to get better performance over the traditional filter. In this paper we propose two new architectures with built in control logic to optimize the power. We use three moduli set {2n -1,2n,2n+1} in the RNS based FIR filter. The circuit is modelled using Verilog HDL,synthesised using RTL compiler and layout is generated using Cadence SoC Encounter in TSMC 180nm technology. © 2016,International Journal of Pharmacy and Technology. All rights reserved.