The clock distribution network primarily comprises of the clock tree and the flip-flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked flip-flops, being the crucial timing elements, have become a major contributor to the total power dissipation. Thus, this study proposes a novel 'self-gated resonant (SGR) clocked flip-flop' to address these concerns. The proposed flip-flop achieves reduced dynamic power dissipation, in addition to the negative setup time, which makes the design more tolerant to the clock skew. This feature also reduces the D-Q delay, thus improving the timing performance of the flip-flop. Second, this study investigates the use of the resonant clock in a hierarchical clock tree distribution network operating 1024 flip-flops at its leaf nodes. The advantages of the SGR clocked flip-flop are validated through exhaustive simulations and comparisons, with the flip-flop structures available in the literature. Furthermore, the post-layout simulations of a typical H-clock tree driving the 1024 flip-flops at the leaf cells have been carried out. Cadence® EDA tools and the 45 nm process technology files have been used to substantiate the merits of the proposed design. © The Institution of Engineering and Technology 2016.