The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The Schematic Edit and T-Spice of Tanner tools formed the simulation environment. © 2006 IEEE.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Salivahanan S

Emmanuel D.S.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Semi-custom design of adiabatic adder circuits

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

A new SRAM cell with better leakage control and enhanced memory retention capability is proposed. The memory array configured using the proposed SRAM cell has all its word lines and bit lines driven adiabatically using differential cascode and pre-resolved adiabatic logic (DCPAL), and it operates as a buffer for the memory array. This paper demonstrates how one of major concerns, namely, the VT variation can be controlled by modifying the ground-line and power-line voltage of the SRAM cell. The designs are implemented using 45-nm technology models operating at a supply voltage of 0.8 V. © Springer Nature Singapore Pte Ltd. 2019.

Integrated Intelligent Computing, Communication and Security Studies in Computational Intelligence

Adiabatic SRAM Cell and Array

The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC. © 2015 IEEE.

2015 Eighth International Conference on Contemporary Computing (IC3)

Two phase sinusoidal power clocked quasi-static adiabatic logic families

Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 x 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %. © 2013 Springer.

Lecture Notes in Electrical Engineering Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)

Design and Implementation of an Efficient Multiplier Using Vedic Mathematics and Charge Recovery Logic

This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

Journal	Data powered by Typeset19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
Publisher	Data powered by TypesetIEEE
ISSN	10639667
Open Access	0