Background/Objective: The memory system occupy a significantly larger area of the SoCs (System on Chip) and it also contributes heavily to the increasing power consumption. The major part of the power consumption is due to the peripheral circuits of the memory systems, with the sense amplifier playing a dominant role, while the memory is accessed for the reading operation. This paper presents a modification of the conventional 6T SRAM cell into the 8T SRAM (Static Random Access Memory) cell memory architecture, focusing on enhancing the writing and reading stability of the memory cell with an additional advantage of providing a separate path for reading the data. Statistical Analysis/Method: To enhance the sensing performance, various sensing schemes such as the domino sensing scheme, AC Coupled sensing scheme and Switching pMOS sense amplifier have been employed. The above mentioned sensing schemes use single bit line for sensing the data. These single ended sensing schemes are implemented and simulated on industry standard Cadence EDA tool using 45nm technology. These are employed for sensing the data from the SRAM banks comprising 8T SRAM cells. Findings: The simulation results show that the power consumption during sensing operation is reduced as compared to traditional sense amplifier due to the advantage of single ended bit line sensing. Conclusion: The investigation and comparison among the three single ended sensing schemes reveals that the switching pMOS sense amplifier exhibits better performance with considerable amount of reduction in sensing power. © 2017 IEEE.