Due to the technology scaling the critical charge stored in active nodes is reducing very drastically, so even very small amount of radiation charge could able to disturb the values stored in the active node. In this paper, we have proposed soft-error tolerant flip flop design. The proposed flip-flop utilizes a cross-coupled inverter on the critical path in the master-stage and generates the required differential signals to facilitate the usage of the Quarto soft-error tolerant cell in the slave-stage. We have also designed the DICE cell and compared the area of both DICE (Dual Interlocked Storage Cell) and Quatro latch. The area required for the quarto latch is lesser than that of DICE cell. Total area decreased in the quarto latch is about 25% that of the DICE latch. The proposed design required only 18 transistors to build the DFF, which is very less as compared to the TSPC (True Single Phase Clocking) DFF and conventional DFF which require 25 and 44 transistors respectively. We have implemented a SEU (Single Event Upset) free 4 bit Johnson counter using the proposed DFF. © 2017 IEEE.