Gate-All-Around Carbon Nanotube Field Effect Transistors (GAA-CNTFETs) based digital logic circuits are studied in this paper for their soft error performance using Cadence simulations. Four different topologies Single Chirality Single Channel (SCSC), Single Chirality Dual Channel (SCDC), Dual Chirality Single Channel (DCSC) and Dual Chirality Dual Channel (DCDC) based digital logic circuits are studied to find out their minimum radiation dose required to flip the digital circuits output. A double-exponential current pulse is induced at respective sensitive node of the digital circuits. The digital gates retain its original state after radiation dose is removed. The simulation result shows SCDC and DCDC based topology for inverter is more reliable because its highest threshold current value is 5.4 µA and 5.8 µA respectively where as SCSC and DCSC topology for inverter is less reliable with lowest threshold current value 2.95 µA and 2.80 µA respectively. In NAND and NOR gate circuits similar result is given in this paper. © IAEME Publication.