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Shifting based VLSI scaler
, Sahoo S.K, Bharathi V, Varma B.S.R.P, Divya V, Kalyan D.
Published in IEEE
Low power and reduced area with high performance digital adder are the main constraints in processors. The main objective of the work is to develop a architecture which reduces the energy consumption of arithmetic modules. Here both the multiplier and divider which perform up scaling and downscaling are embedded in a single shifting based architecture so that the area gets reduced and the power also reduces obviously. Division is done by shifting and subtracting technique and multiplication also done by using the same shifter and adding technique to reduce the total area and power with better performance. The speed of scaling is based on addition and subtraction operations speed in this architecture which are limited by carry and borrow propagations. Carry select adder without multiplexer adder is used here in this architecture to overcome the speed limitation. Carry select adder without multiplexer has less area and propagation delay which in term gives better performance addition and subtraction. Validation of proposed design is done by designing and implementing it for a 16 bit scaler. To prove its efficiency it is compared with existing division and multiplication architectures. The performance analysis shows that the proposed architecture achieves more advantages than other architectures. The techniques used here can be used or applicable to a variety of arithmetic modules which have similar characteristics. © 2015 IEEE.
About the journal
JournalData powered by Typeset2015 IEEE 9th International Conference on Intelligent Systems and Control (ISCO)
PublisherData powered by TypesetIEEE
Open AccessNo