This paper presents the implementation of a tree adder structure using the single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic) . This static adiabatic logic has proved its advantage through the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits found in the literature. The Sklansky tree adder structure has been chosen due to its increased fan-out that results in reduced latency and improved speed performance. Firstly, the performance characteristics of CEPAL tree adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The CEPAL being a static type of adiabatic logic, its performance is also compared against the Clocked Adiabatic Logic, which is a dynamic type of adiabatic logic. The analyses are carried out using the industry standard EDA design environment using 180 nm technology library from TSMC. The results prove that CEPAL adiabatic tree adder results in 25% of power savings over static CMOS. On the other hand, the dynamic adiabatic tree adder using CAL results in power savings of 72% over static CMOS at 100 MHz. © 2012 IEEE.