With the evolution of CMOS technology, scaling continues to play an important role. This requires the transistor to operate at low supply voltages. However, the threshold voltages do not decrease at the same rate as the supply voltage VDD, resulting in reduced output swing. Besides, the second order effects will be more predominant with scaling. In addition, the intrinsic gain available from the transistors is lessening. This trend makes the traditional techniques, like cascoding and gain boosting, unproductive for achieving high DC gain in nano-scale CMOS processes. Consequently, horizontal cascading multi-stage must be used in order to realize high-gain op-amps in low-VDDprocesses. One major hardship in doing so is the trade-off between gain and stability. With multi-staging, gain increases at the cost of stability of the system. In order to achieve better stability, there is a need for op-amp compensation. This paper presents the design of op-amp using split-length compensation and compares its performance with Miller compensation. The gm/ID methodology is used for the design purpose which includes the second order effects of the transistors. The designed circuit is simulated in Cadence Virtuoso schematic editor using 180 nm CMOS technology. The results of Split length technique show an improvement of 18.2% in gain and 37.5% in phase margin with a significant reduction in the area along with an increase in the speed of the circuit as compared to the Miller Compensation technique. © 2018 IEEE.