The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model. © 2021, Springer Nature B.V.