This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Raina J.P.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

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Two-phase sinusoidal power-clocked quasi-adiabatic logic circuits

Journal of Circuits, Systems and Computers

This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.

Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures

This paper presents FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Its efficiency is proved through half and full adder circuits constructed using FinFET-based 2N2P, 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) and Pass transistor Adiabatic Logic (PAL) based circuits. Carry Lookahead Adder (CLA) and Carry Save Multiplier (CSM) are used as benchmark circuits to validate the efficiency of EEPAL. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. BSIMCMG FinFET models have been used for simulations in Cadence® Virtuoso. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL. © 2019 Elsevier Ltd

Microelectronics Journal

Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

This paper introduces a novel design methodology i.e. adiabatic subthreshold mode which inherits the features of both the subthreshold logic and the adiabatic (or the energy recovery) circuits. In this paper, analysis of essential digital gates is done for the three modes of operation namely, (1) subthreshold (2) adiabatic and (3) adiabatic subthreshold operation. The simulation results validate the benefits obtained in terms of the reduced energy consumption in the adiabatic subthreshold mode, making it suitable for ultra low power and medium throughput (10 kHz–1 MHz) applications. Specifically, it has been emphasized that the non-adiabatic dissipation that is prevalent in adiabatic circuits is almost discarded in the proposed mode. And, the challenges faced by the methodology are mitigated by the circuit level technique of upsizing the channel. Berkeley Predictive Technology Model (BPTM) 45 nm technology node has been used in the simulation studies on industry standard Spice tools. © Springer India 2016.

Lecture Notes in Electrical Engineering Microelectronics, Electromagnetics and Telecommunications

Subthreshold Operation of Energy Recovery Circuits

The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC. © 2015 IEEE.

2015 Eighth International Conference on Contemporary Computing (IC3)

Two phase sinusoidal power clocked quasi-static adiabatic logic families

This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies. Copyright © 2008 American Scientific Publishers All rights reserved.

Journal of Low Power Electronics

Differential Cascode Adiabatic Logic Structure for Low Power

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The Schematic Edit and T-Spice of Tanner tools formed the simulation environment. © 2006 IEEE.

Journal	Journal of Circuits, Systems and Computers
Publisher	World Scientific Pub Co Pte Lt
ISSN	0218-1266
Open Access	0