The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal transition demands a change in the state of the output. Or in other words, if the next input state happens to be the same as the present state, the charged output nodal state remains the same, without undergoing any recovery phase. The analysis of the static adiabatic logic is done using a carry look ahead adder (CLA) implemented by static adiabatic families, namely, QSERL, CEPAL, ASL and QSECRL and comparing them against the static CMOS counterpart. The performance of each of the circuit is studied in terms of the frequency and power clock voltage range of operation. The simulations show that the 8-bit CLA static adiabatic adder realizes energy reduction from 45% to 83% over a frequency range of 100 KHz to 500MHz operation against the static CMOS implementation. The analyses were carried out using SPICE EDA tools using 180 nm technology library from TSMC. © 2015 IEEE.

Sasipriya P

Electrical

School of Electrical Engineering

Chennai Campus

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Two phase sinusoidal power clocked quasi-static adiabatic logic families

2015 Eighth International Conference on Contemporary Computing (IC3)

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

Journal of Circuits, Systems and Computers

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

This paper presents the implementation of a tree adder structure using the single phase clocked quasi static adiabatic logic namely CEPAL (Complementary Energy Path Adiabatic Logic) [7]. This static adiabatic logic has proved its advantage through the minimization of the 1/2CVth2 energy dissipation occurring every cycle in the multi-phase power-clocked adiabatic circuits found in the literature. The Sklansky tree adder structure has been chosen due to its increased fan-out that results in reduced latency and improved speed performance. Firstly, the performance characteristics of CEPAL tree adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The CEPAL being a static type of adiabatic logic, its performance is also compared against the Clocked Adiabatic Logic, which is a dynamic type of adiabatic logic. The analyses are carried out using the industry standard EDA design environment using 180 nm technology library from TSMC. The results prove that CEPAL adiabatic tree adder results in 25% of power savings over static CMOS. On the other hand, the dynamic adiabatic tree adder using CAL results in power savings of 72% over static CMOS at 100 MHz. © 2012 IEEE.

2012 International Conference on Devices, Circuits and Systems (ICDCS)

Single phase clocked quasi static adiabatic tree adder

This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

TWO-PHASE SINUSOIDAL POWER-CLOCKED QUASI-ADIABATIC LOGIC CIRCUITS

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The Schematic Edit and T-Spice of Tanner tools formed the simulation environment. © 2006 IEEE.

Journal	Data powered by Typeset2015 Eighth International Conference on Contemporary Computing (IC3)
Publisher	Data powered by TypesetIEEE
Open Access	No