Validation of Automated Test Cases with Specification Path
Software development life cycle (SDLC) contains different phases. Software testing life cycle (STLC) has to be spent more time and cost during the development of embedded system software. Test cases are paly the major role in the embedded system software testing. Design specifications based automated test case has the added benefit of permitting test cases to be accessible timely in the software development life cycle. The validation process has reduced the effort in SDLC. Specification designs of the embedded system offer effective evidence during the software development process. Specification path based validation of automated test cases is improving the productivity of embedded system software. This paper presents a method for validation of automated test cases using specification path of embedded system. It makes three major processes. First, specification diagrams are converted to event flow graph and then nodes and edges are minimized using timed event flow path, finally the automated test cases are validated with the flow path of the EFG. This paper has accessible our proposed method with examples of real-time embedded system software.
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|Journal||Data powered by TypesetJournal of Statistics and Management Systems, Issue on Machine Learning and Software Systems|
|Publisher||Data powered by TypesetTaylor and Francis|