System-on-a-Chip (Soc) design has become more complex, because many functional components or IPs (Intellectual Property) will be integrated within a chip. The test of integration is 'how to verify on-chip communication properties'. Since conventional simulation-based bus protocol monitors can validate whether bus signals obey bus protocol or not, but they often lack of efficient debugging techniques. This paper mainly focuses on verifying the important features of advanced extensible interface (AXI). Validation of AXI design using System Verilog, Validating the transactions of AXI includes thevalidation of all the five channels read address, read data, write address, write data and write response. © 2017 IEEE.