This paper mainly focuses on verifying the important features of advanced extensible interface (AXI). Verifying the memory transactions of AXI includes the verification of all the five channels write address, write data, write response, read address and read data. In this work a Verification Intellectual Property cores (VIP) based methodology is used to carry out the verification Process. In the VIP design the entire test environment is modeled using system verilog and the read, write transactions from the same and different memory locations has been verified with the quantitative values of Busy Count, Valid Count and its Bus Utilization. Verifying the System connectivity during write and read cycles is also one of the fundamental features verified in this paper. © 2015 IEEE.

Mahesh Ganesapillai

Department of Chemical Engineering

School of Chemical Engineering

Vellore Campus

Sakthivel S M

Electronics

School of Electronics Engineering

Chennai Campus

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Verification of memory transactions in AXI protocol using system verilog approach

2015 International Conference on Communications and Signal Processing (ICCSP)

Objective: In this paper, the design and verification of AMBA AXI3 protocol are carried out in a coverage mode analysis using Verilog HDL language. Method: The design of AXI protocol is made according to its architecture specifications, and its functionality is verified using QuestaSim tool. In the AXI protocol analysis, the burst-based transactions, i.e. writing and reading of increment burst have been implemented. Findings: In addition to that the AMBA AXI efficiency is evaluated by calculating performance metrics bus utilization, busy count and valid count. In the entire paper, a verification environment is created for the verification of AXI protocol as a verification IP for modern SOC architectures. Applications: High percentage of bus utilization ensures that the SOC on chip bus is functioning well and makes this protocol as one of the widely used protocols in today’s SOC implementation. © Springer Nature Singapore Pte Ltd. 2018.

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Design and Verification of AMBA AXI3 Protocol

System-on-a-Chip (Soc) design has become more complex, because many functional components or IPs (Intellectual Property) will be integrated within a chip. The test of integration is 'how to verify on-chip communication properties'. Since conventional simulation-based bus protocol monitors can validate whether bus signals obey bus protocol or not, but they often lack of efficient debugging techniques. This paper mainly focuses on verifying the important features of advanced extensible interface (AXI). Validation of AXI design using System Verilog, Validating the transactions of AXI includes thevalidation of all the five channels read address, read data, write address, write data and write response. © 2017 IEEE.

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

Validation of transactions in AXI protocol using system verilog

Computers & Electrical Engineering

Design and verification of an efficient WISHBONE-based network interface for network on chip

Microprocessors and Microsystems

Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test

Multi-core software/hardware co-debug platform with ARM CoreSight&#x2122;, on-chip test architecture and AXI/AHB bus monitor

2010 IEEE Computer Society Annual Symposium on VLSI

A High Throughput Low Power FIFO Used for GALS NoC Buffers

IEEE Transactions on Parallel and Distributed Systems

A True O(1) Parallel Deadlock Detection Algorithm for Single-Unit Resource Systems and Its Hardware Implementation

Journal	Data powered by Typeset2015 International Conference on Communications and Signal Processing (ICCSP)
Publisher	Data powered by TypesetIEEE
Open Access	No