This paper focuses on implementing Linear convolution algorithm using Vedic Mathematics to achieve higher speed and low power. Vedic Mathematics is an ancient Indian System for performing calculation. The Vedic multiplier is designed by using the Urdhava Triyagbhayam sutra. The use of Vedic Mathematics is made because it reduces the steps and time consumed in computation of partial products. In the proposed method, this process is done in a single step. The multiplier is designed in Verilog, simulation is done in Xilinx, and synthesis is done in RTL compiler using Cadence. This multiplier is then used to perform operations on complex numbers, convolution. The design process proposed in this paper is limited to 8 Bit inputs. The technology used for synthesis is 45 nm. © Research India Publications.