By virtue of its non-linear switching characteristics manifested by ionic percolation in the solid lattice under the influence of applied voltage, memristor is regarded as non-volatile memory (NVM) otherwise known as resistive random access memory (RRAM). It possesses promising characteristics such as low power, non-volatility, high density and multi-level functions to replace the present CMOS gates and memories. Nevertheless, it is greatly affected by process variations, particularly variation in thickness. Fault analysis proves that there are number of stability faults occur in addition to other typical memory faults. This research work presents a novel built-in self-test techniques to test the weak memory cells in memristor memory arrays. The basic idea is to create electrical stress to the cells such that the strong cells will retain its state while the weak cells expected to flip its state. Most of the design for testability (DFT) techniques employ the deterministic test patterns algorithm like March tests. Though March tests are very effective for the conventional memories, they are not so effective in case of memristor-based memories. Stability faults such as the undefined state faults cannot be sensitized using the conventional March test patterns. Thus, to enhance the fault coverage, new weak read and weak write mode approaches namely short refresh time (SRT), short write time (SWT) and low write voltage (LWV) are to be employed in the test sequence. Cadence Spectre gpdk180 library and memristor linear ion drift model with Biolek window function were used to perform the stability fault injection and circuit functional simulation. © 2018, Springer Nature Singapore Pte Ltd.