Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique. © The Institution of Engineering and Technology.

Bindu B

Electronics

School of Electronics Engineering

Chennai Campus

Ramaniharan P.K

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

IET Circuits, Devices & Systems

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson's equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter. © 1963-2012 IEEE.

IEEE Transactions on Electron Devices

An Analytical Model of Single-Event Transients in Double-Gate MOSFET for Circuit Simulation

Single event transient (SET)due to heavy-ion strike is one of the serious reliability issues when the MOSFET is scaled down to advanced technology nodes. SOI technology is more immune to SET than bulk technology due to its smaller collection volume and buried oxide (BOX). The device structure modification using thin BOX and ground plane (GP)doping will aid further scaling of SOI MOSFET. In this paper, the bipolar amplification due to heavy-ion strike is analysed for both thick BOX device and thin BOX device with GP in 45 nm SOI technology. The bipolar gain is reduced by optimizing GP doping. The effect of substrate bias and supply voltage scaling on the bipolar gain is also analysed. The replacement of thick BOX with thin BOX (without GP)reduces the bipolar gain by 3.2 times for LET = 0.2 MeV/(mg/cm2). The inclusion of a GP layer underneath the thin BOX reduces the bipolar gain further by 2.3 times. This lower bipolar amplification of thin BOX with GP device makes it to be less sensitive to the heavy-ion strike than the one with thick BOX. © 2019 Elsevier Ltd

Microelectronics Reliability

Analysis of bipolar amplification due to heavy-ion irradiation in 45 nm FDSOI MOSFET with thin BOX and ground plane

Electronic circuits operated in radiation environment such as space are adversely affected by the ionizing radiation. The effects include generating a transient current, altering threshold voltage and other device characteristics, and lattice damage. Of these, transient current can result in immediate change in device/circuit behaviour resulting in malfunction. This will be recoverable based on the energy and type of the ion. Thus, a better understanding of single-event effects is very important to operate the electronic circuits in the radiation environment. This paper reviews the existing methodologies to simulate the propagation of single-event transient (SET) in digital circuits and their shortcomings. An improved simulation methodology which can reproduce even the tail portion of the SET current as observed in three-dimensional technology computer aided design (TCAD) mixed-mode simulations is also proposed in this paper. This is obtained by modifying an existing simulation technique based on switch and resistor using varying resistance. The proposed technique is simple and easy to implement the SET propagation in any circuit simulator. After integrating this proposed simulation technique in circuit simulator SPECTRE, the propagation of SET, and its effects in delay locked loop (DLL) are analysed. The strike of SET in voltage-controlled delay line (VCDL) results in duty cycle error and missing clock pulse error at the DLL output. Also, the results show that the first few stages of the VCDL are more vulnerable than the rest for LETs (linear energy transfer) more than 60 MeV-cm2/mg. For LETs less than 60 MeV-cm2/mg, last delay stage has more vulnerability. © 2017 IETE.

IETE Technical Review

A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop

International Journal of Recent Trends in Engineering and Research

Printed Circuit Board design for Inverting Summing Amplifier using CADENCE

3D TCAD Simulation for CMOS Nanoeletronic Devices

Introduction of Synopsys Sentaurus TCAD Simulation

IEEE Transactions on Nuclear Science

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Modeling Single Event Transients in Advanced Devices and ICs

Widening and narrowing of time interval due to single-event transients in 45 nm vernier-type TDC

Journal	IET Circuits, Devices & Systems
Publisher	Institution of Engineering and Technology (IET)
ISSN	1751-858X
Open Access	0