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V S Kanchana Bhaaskaran
Professor - Higher Academic Grade
Electronics
kanchana.vs@vit.ac.in (Work)
vskanchana@ieee.org (Work)
vskanchana@gmail.com (Work)
+91-9791179275 (Work)
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Publications - 89
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Publications (89)
Network (11)
Publications (89)
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Book Chapter
Quantum Cost Optimization of Reversible Adder/Subtractor Using a Novel Reversible Gate
B. P. Bhuvana
and
V S Kanchana Bhaaskaran
2018 | Springer Singapore
Book Chapter
High Performance Domino Logic Circuit Design by Contention Reduction
Anita Angeline A
and
V S Kanchana Bhaaskaran
2018 | Springer Singapore
Proceedings Article
Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack
Bhuvana B. P.
and
V S Kanchana Bhaaskaran
2018 | IEEE
Other
Preface
V. Madhu
,
A. Manimaran
,
...
,
Vetrivelan P
,
...
,
Mubashir Unnissa M
,
Venkata Lakshmi Narayana K
and
V S Kanchana Bhaaskaran
(8 authors)
2018 | Springer International Publishing
Journal Article
Design and Implementation of 32-Bit High Valency Jackson Adders
Poornima T
and
V S Kanchana Bhaaskaran
2017 | World Scientific Pub Co Pte Lt
Journal Article
Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique
Bhusare S.S
and
V S Kanchana Bhaaskaran
2017 | World Scientific Pub Co Pte Lt
Proceedings Article
DPA resistance analysis of the cryptographic S-box implementation in static CMOS and TDPL logic style
Chintalapudi satish kumar
,
Prathiba A
and
V S Kanchana Bhaaskaran
2017 | IEEE
Journal Article
Energy Recovery Logic using FinFET
Shatakshi Panda S
,
Judy D.J
and
V S Kanchana Bhaaskaran
2017 | Elsevier BV
Proceedings Article
ALU design using Pseudo Dynamic Buffer based domino logic
Siva kumar akurati
,
Anita Angeline A
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Multiphase pipelining in domino logic ALU
Swati verma
,
A anita angelina
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Optimization of power and energy in FinFET based SRAM cell using adiabatic logic
Sudarshan patil
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Design of novel Multiple Valued Logic (MVL) circuits
B srinivasa raghavan
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Design of process variation tolerant domino logic keeper architecture
Shyamali padhi
,
Anita Angeline A
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Clock distribution network design for single phase energy recovery circuits
Nunna yamini
,
Sasipriya P
and
V S Kanchana Bhaaskaran
2017 | IEEE
Journal Article
Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET
Bhuvana B.P
and
V S Kanchana Bhaaskaran
2017 | Elsevier BV
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Publisher Copy
Proceedings Article
Sensing schemes of sense amplifier for single-ended SRAM
Ameya chandras
and
V S Kanchana Bhaaskaran
2017 | IEEE
Proceedings Article
Improved read noise margin characteristics for single bit line SRAM cell using adiabatically operated word line
Ayon manna
and
V S Kanchana Bhaaskaran
2017 | IEEE
Journal Article
Open Access
FPGA Implementation and Analysis of the Block Cipher Mode Architectures for the PRESENT Light Weight Encryption Algorithm
Prathiba A
and
V S Kanchana Bhaaskaran
2016 | Indian Society for Education and Environment
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PDF
Publisher Copy
Proceedings Article
Standard Cell Characterization for Reversible Logic
Bhuvana B.P
,
Manohar B.R
and
V S Kanchana Bhaaskaran
2016 | IEEE
Journal Article
Low Power, High Speed and Area Efficient Binary Count Multiplier
Dattatraya K.S
,
Appasaheb B.R
,
...
,
V S Kanchana Bhaaskaran
(4 authors)
2016 | World Scientific Pub Co Pte Lt
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