Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

H.264 and H.265 are the most popular video coding standards used for various applications. These coding standards use multiple modules to perform video compression. Among the various modules, the deblocking filter (DBF) is one of the critical modules in the video codec, which requires extensive computation. It is computationally complicated and critically time-consuming. DBF removes the blocking artefacts caused due to inverse transform, intra-prediction, inter-frame prediction and motion compensated prediction. For the past two decades, the deblocking filtering algorithm is implemented in hardware and research is still going on for realising optimised hardware solutions for this critical module. Efficient hardware implementation of the DBF is essential for high-resolution video applications such as HDTV to increase the decoding throughput, to achieve high speed and to reduce the off-chip memory access cycles. This paper presents an intricate analysis of various hardware architectures of DBF used for H.264 and H.265 coding standards. Copyright © 2020 Inderscience Enterprises Ltd.

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

International Journal of Materials and Product Technology

Analysis of hardware implementations of deblocking filter for video codecs

High-Efficiency Video Coding (HEVC/H.265) is the latest video coding standard used in various applications. In HEVC, the quality of the reconstructed video is enhanced by two in-loop filters (Deblocking filter and Sample Adaptive Offset filter). In this paper, we propose an efficient resource sharing hardware architecture for deblocking filter. This architecture utilizes four edge filters to filter two edges of the 8 × 8 block in parallel. The edges are filtered following the sequential filter ordering. The proposed architecture is implemented in Verilog HDL and synthesized using Synopsys DC. The simulation results show that this architecture can process a 16 × 16 block in 45 clock cycles and hence an LCU in 720 clock cycles. It utilizes an area of 93.5 K in 32 nm technology supporting UHD video which is suitable for real-time applications. Copyright © 2019 The Institute of Electronics, Information and Communication Engineers

Fulltext

IEICE Electronics Express

Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

IEEE Access

High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems

Motion estimation one of the advanced technique adapted in the industry for video coding and implemented in various applications. This work is focused on the efficient hardware implementation of the diamond search algorithm architecture. Among all the other Fast Search algorithms like three-step search, new three-step search, four-step search and diamond search (DS), the diamond search algorithm maintains the diamond shape search pattern and it gives faster search pattern and minimum absolute difference. When compared with the original diamond search (DS) algorithm, this modified diamond search algorithm requires less area and power maintaining the same performance. Other than the architectural level changes the low power synthesis is done and the results show that this design can be implemented effectively for an application that require fast search with low power requirements like IoT and sensor devices. The design has been implemented using Verilog HDL, synthesized using Synopsys DC compiler using 90nm technology.

International Journal of Engineering & Technology

Hardware Implementation of Diamond Search Algorithm for Motion Estimation

In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is a crucial module/block which plays a major role in computing the efficiency of video coding. Because of variable block size in H.264, motion estimation becomes more complex and requires most efficient hardware for implementation in real-time video coding. The hardware implementation of SAD is done using Comparator and Carry skip adder. The comparator is used to implement the absolute difference unit, which is used to calculate the absolute difference values between each pixel of the current frame and the reference frame. Carry skip adder is used to add all the output values of the absolute difference unit. Carry skip adder improves the performance of the arithmetic operation. It does not wait for carrying to propagate which helps in increasing the speed of operation of adding. Comparator and Carry skip adder unit improves the performance of SAD calculation in terms of speed, area, and power. We had also proposed a control unit for H.264 video. This proposed control unit calculates the SAD output values according to block size given as input to control unit.

VIT Unitversity

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

A SAD architecture for variable block size motion estimation in H.264 video coding

Edge Detection is an ever-expanding frontier in the field of Digital Image Processing. Several research papers have been published in this domain in the past decade specifying many applications of edge detection methods using platforms like MATLAB or OpenCV like Hough, Canny, Sobel, Prewitt Trans- forms among many others. In this case study, various elaborations on basic methods of edge detection have been made and their applications have been discussed in real-time. Furthermore, the performance analysis is figure out by comparison between the results of Canny Edge Detection method and Hough Transforms. © IAEME Publication.

Department of Embedded Technology

Department of Control and Automation

School of Electrical Engineering

World University root node

International Journal of Mechanical Engineering and Technology

A case study: Edge detection techniques using hough transform and canny edge algorithm

In the due course of time, due to rising development cost and density of VLSI chips and turnaround time, it turns out to be critical to have a verification methodology, which empowers first pass chips to be entirely functional and error free. Universal Verification Methodology (UVM) facilitates the communication through TLM interface. On account of its excellent architecture of AMBA and simplicity of AHB bus it has been widely used in several SOC designs. This paper is focused on developing a Verification IP (VIP) for Multi-master AMBA AHB protocol using System Verilog based UVM environment. AMBA-AHB provides a high bandwidth system bus which can perform multiple operations in parallel. This project also depicts how Verification IP is used to verify the AHB Components-Arbiter, Slave, Master and Decoder. With the UVM based VIP, it was able to achieve MDV (Metric Driven Verification) and assertion based verification which has drastically minimized the time spent on verification of a design.The Verification IP is developed using Cadence tool Ncsim and can be reused to verify any AHB based system design.

International Journal of Chemical Sciences

Multi-Master amba ahb protocol verification using tlm based uvm environment

In our day today life, we see that most of the people fall down when the situations are not normal. The abnormal situations can be either due to sickness or due to sudden injury. Sickness can be a chest pain, faint, vomiting, headache, etc., and sudden injury can be due to sudden fall on the ground due to slippage, fire accident, etc., Analysis shows that most of the abnormal situations of the humans are accompanied by a fall from their original or normal position. The fall of elderly people has become more common and the injuries caused by fall may be so severe such that the person may not be in a position to ask for help, which may be life threatening too. Hence the detection of a fall which is an abnormal activity from the normal human activity is more important for automated geriatric care and health care systems. The algorithm used to detect the abnormal human activity should be accurate because the normal activities should not be detected as an abnormal activity. In this paper, a review is made on the automated fall detection systems used for smart home systems and for automated health care systems.