Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP. © 2020, Springer-Verlag GmbH Germany, part of Springer Nature.

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Journal of Ambient Intelligence and Humanized Computing

Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

Decimal arithmetic is receiving greater attention due to its applications in banking and internet-based sectors. Several algorithms have been introduced for Multi-operand addition. A mixed approach of having binary adders followed by binary to BCD converter is showing better performance compared to binary adders with correction logic in intermediate stages. Adder circuits form the basis of our computing. Multiplication and division algorithms are also based on the adder circuits. Thus designing fast Multi-operand parallel adders is receiving greater interest by researchers. BD converters that are the final blocks of the adder circuits have gained a lot of importance highlighting the need to have an efficient BD converter as critical for improvised adder architectures. This paper proceeds with the mixed approach and it considers the special case of 8 operand decimal addition which is done using binary CSA structure and proposes a BD converter for 7-bit binary number that is efficient in terms of area and delay when compared to the existing designs. The power delay product of our design is 27% more efficient than existing designs. © 2019 IEEE.

VIT Unitversity

2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN)

Delay Optimized Binary to BCD Converter for Multi-operand Parallel Decimal Adder

In finance transactions and tax calculation the binary coded adder (BCD) are preferred than binary adders. The conventional BCD adder has two four-bit binary adders. One is used for finding the binary-sum and the other for the decimal sum. The conventional BCD adder has a huge carry delay due to the presence of a four-bit binary adder in the binary-sum stage. The technique proposed in this work provides a solution for this problem. In the proposed design, only one four-bit binary adder is used at the end of the process. A new method is proposed for determining the decimal carry of the BCD adder. The feature of the proposed design is that the decimal carry is calculated in two gate delays, except for the first digit. The synthesis results show that the proposed circuit generates the final sum around 3.5 times faster than conventional 32-digit BCD adder. The proposed design provides an area overhead of 0.68 times the conventional, while the power consumption remains the same. © BEIESP.

International Journal of Engineering and Advanced Technology

A high-speed BCD adder using single 4-bit binary adder and detector circuit

Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier. © 2019 IEEE.

An Area Efficient 16-bit Logarithmic Multiplier

In this paper, A Low Power Pre-charge Free Dynamic Content Addressable Memory is Proposed, it is one of the most significantly used Hardware search Engine in Modern Computing, Security Systems and in areas needing fast Memory Access. It is not only a Data Storage Device but also designed to search its own memory in single Cycle. The CAM is introduced in low power Parallel look up search Applications. A Proposed Low Power 6-T DCAM cell consuming power less than 93% and 43% than PF-DCAM and PF-CAM cells is introduced in Hardware Search Engine. 8∗8 CAM Architecture of the proposed scheme is implemented using Cadence GPDK 45nm Technology. © 2019 IEEE.

Low Power Pre-Charge Free DCAM

In this paper a current fed interleaved DC-DC boost converter which has an isolated topology and used for high voltage step up is proposed. A basic DC to DC boost converter converts uncontrolled DC voltage into controlled DC voltage of higher magnitude. Whereas this topology has the advantages of lower input current ripple, lesser output voltage, lesser stress on switches, faster transient response, improved reliability and much lesser electromagnetic emission over the conventional DC to DC boost converter. Most important benefit of this interleaved DC to DC boost converter is much higher efficiency. The input current is divided into two paths, substantially ohmic loss (I2R) and inductor ac loss gets reduced and finally the system achieves much higher efficiency. With recent mandates on energy saving interleaved DC to DC boost converter may be used as a very powerful tool to maintain good power density keeping the input current manageable. Higher efficiency also allows higher switching frequency and as a result the topology becomes more compact and cost friendly. The proposed topology boosts 48v DC to 200 V DC. Switching frequency is 100 kHz and PSIM 9.1 Platform has been used for the simulation. © Published under licence by IOP Publishing Ltd.

Department of Energy and Power Electronics

School of Electrical Engineering

Fulltext

IOP Conference Series: Materials Science and Engineering

Design and dSpace interfacing of current fed high gain dc to dc boost converter for low voltage applications

Background/Objectives: XOR gate is a primary element in binary adders because which is used to detect sum - output. Inthis paper a 2-input XOR gate is accomplished by a modified design. Methods/Statistical Analysis: Usually a Half Adder(HA) circuit is designed with one XOR and one AND gate but if this modified XOR is used in HA, the design requires onlyone XOR gate and the AND gate can be acquired from XOR gate itself. Findings: This modified XOR gate design gives betterresult when the adder circuit has more number of XOR gates, so we used this modified XOR gate in conventional sqrt CSLA,Binary to Excess-1 Converter (BEC) based sqrt CSLA and Optimized Logic Based (OLB) sqrt CSLA. The results show thatArea - Delay - Product (ADP) has been reduced in proposed circuits, 12.45% in conventional sqrt CSLA, 21.45% in BECbased sqrt CSLA and 17.81% in OLB sqrt CSLA. Applications/Improvements: These adders can be used in ArithmeticLogic Unit (ALU) of a micro-processor as a binary adder.