Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

VIT Unitversity

Department of Information Security

School of Computer Science and Engineering

Vellore Campus

Advances in Intelligent Systems and Computing Intelligent Systems Design and Applications

Accelerating Image Encryption with AES Using GPU: A Quantitative Analysis

Object detection is not only shaping how Computers see and analyze things but it is also helping in the behavior of how an object reacts to the change in its environment. The main application of these object detection sensors or software is to find the location of an object in space or to track its movement. Object detection has infinitely many use cases and in this paper, we are introducing an application that will allow safety of users struck in a disaster and who need to be evacuated. In such cases the main thing to focus and to eradicate is camera noise, saturation and image compression. Our solution is to establish a connection between the person struck in a disaster with fire safety people. This works over a convolutional network that allows us to detect vulnerable things present inside a room that needs to be rescued and can also give an insight of any explosive inside the room. Our model uses Faster-RCNN and COCO which is a pretrained dataset. This allows real time object detection and classification on our network. Using this we were able to detect an object or a person and get him to rescue by providing them a shortest way out of that place. With this we were able to get an accuracy of more than 75% in our object detection model. © 2020 IEEE.

World University root node

International Conference on Emerging Trends in Information Technology and Engineering, ic-ETITE 2020

Real Time Object Detection in Surveillance Cameras with Distance Estimation using Parallel Implementation

Cloud storage services are quickly increasing and more prevalent. CSP-cloud storage providers offer storage as a service to all the users. It is a paid facility that allows association to outsource their confidential data to be stored on remote servers. But, identity privacy and preserving data from an untrusted cloud is a difficult concern, because of the successive change of the members. CSP has to be secured from an illegitimate person who performs data corruption over cloud servers. Thus, there is a need to safeguard information from the individuals who don’t have access by establishing numerous cloud storage encryption plans. Every such plan implemented expects that distributed storage suppliers are protected and can't be hacked; however, practically speaking, a few powers will compel distributed storage suppliers to render client details and secret information on the cloud, in this manner inside and out bypassing stockpiling encryption plans. In this paper, a new scheme is introduced to protect user privacy by a deniable CP_ABE(Cloud Provider_ Attribute Based Encryption) scheme which implements a cloud storage encryption plan. Since coercers cannot specify whether privileged insights are valid or not, the CSP ensures privacy of the user

Department of Smart Computing

School of Information Technology and Engineering

Department of Information Technology

Department of Software and Systems Engineering

VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE International Journal of Innovative Technology and Exploring Engineering

Secure and Error-Free Data Storage on Cloud via Deniable CP-ABE Scheme

With the growth of data parallel computing, role of GPU computing in non-graphic applications such as image processing becomes a focus in research fields. Convolution is an integral operation in filtering, smoothing and edge detection. In this article, the process of convolution is realized as a sparse linear system and is solved using Sparse Matrix Vector Multiplication (SpMV). The Compressed Sparse Row (CSR) format of SPMV shows better CPU performance compared to normal convolution. To overcome the stalling of threads for short rows in the GPU implementation of CSR SpMV, a more efficient model is proposed, which uses the Adaptive-Compressed Row Storage (A-CSR) format to implement the same. Using CSR in the convolution process achieves a 1.45x and a 1.159x increase in speed compared to the normal convolution of image smoothing and edge detection operations, respectively. An average speedup of 2.05x is achieved for image smoothing technique and 1.58x for edge detection technique in GPU platform usig adaptive CSR format.

International Journal of Grid and High Performance Computing

GPU Implementation of Image Convolution Using Sparse Model with Efficient Storage Format

Advances in Intelligent Systems and Computing Proceedings of International Conference on Computer Vision and Image Processing

Parallel Implementation of RSA 2D-DCT Steganography and Chaotic 2D-DCT Steganography

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Indian Journal of Science and Technology

A Survey of Performance Analysis Tools for OpenMP and MPI

2016 International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)

Comparative study on Boruvka's implementation on hetrogenous platform with cache analysis

The advent of Multi-core processors has offered powerful processing capabilities and provided new avenues for parallel processing. As the traditional methods of computation are inherently based on single core of execution, they are not capable of taking the advantage of high computational power offered by multi core processors, even if available. Singular Value Decomposition (SVD) has been proven well for many image processing techniques such as image compression, quality measure and in watermarking. SVD is a highly compute intensive algorithm that applies numerous matrix operations to an image such as transpose, inverse, multiplication of high orders to form a compressed image. However accelerating the SVD routines to exploit the underlying hardware poses a significant challenge to the programmers. This paper deals with improving the speedup of SVD algorithm used in image compression technique. This is achieved by identifying the areas where data parallelism can be applied and parallel programming model OpenMp is used to run the parallel components on multiple processors. This results in faster execution of the algorithm and hence reduces the execution time when applied to image compression for large images. This paper also addresses the space overhead of storing the matrices of SVD technique, by adapting efficient sparse matrix storage format such as Compressed Row Storage (CSR). Experimental results show that the speedup achieved through OpenMp is around 1.15 and better compression ratio with sparse matrix storage format.

Parallel Implementation of Singular Value Decomposition (SVD) in Image Compression using Open Mp and Sparse Matrix Representation

Performance improvement in modern processor is staggering due to power wall and memory wall problem. In general, the power wall problem is addressed by various vectorization design techniques. The Memory wall problem is diminished through prefetching technique. In this paper vectorization is achieved through Single Instruction Multiple Data (SIMD) registers of the current processor. It provides architecture optimization by reducing the number of instructions in the pipeline and by minimizing the utilization of multi-level memory hierarchy. These registers provide an economical computing platform compared to Graphics Processing Unit (GPU) for compute intensive applications. This paper explores software prefetching via Streaming SIMD extension (SSE) instructions to mitigate the memory wall problem. This work quantifies the effect of vectorization and prefetching in Matrix Vector Multiplication (MVM) kernel with dense and sparse structure. Both Prefetching and Vectorization method reduces the data and instruction cache pressure and thereby improving the cache performance. To show the cache performance improvements in the kernel, the Intel VTune amplifier is used. Finally, experimental results demonstrate a promising performance of matrix kernel by Intel Haswell's processor. However, effective utilization of SIMD registers is a programming challenge to the developers.

Exploring Vectorization and Prefetching Techniques on Scientific Kernels and Inferring the Cache Performance Metrics

As the field of Sparse Matrix vector multiplication (SpMV) matures and its breadth of application increases, the need for parallel implementation becomes necessary. SpMV is proved to be a bottleneck due to its irregular access patterns. Various storage formats for sparse matrices have been proposed to solve this issue. The Quad tree-Compressed Row Storage (QCSR) format shows good performance improvement over other formats such as Compressed Row Storage (CSR) and Blocked CSR (BCSR) for SpMV. This paper extends QCSR format to exploit the Single Instruction Multiple Data (SIMD) registers which are available in current processors. Programming with SIMD registers in a single core processor achieves parallelism with reduced power and without any additional hardware requirement, as in the case of Graphics Processing Unit (GPU) computing. To program effectively in SIMD units Intels Streaming SIMD Extension (SSE) instructions are used. In this paper computational performance of QCSR-SpMV is determined for over a collection of 10 benchmark matrices on SIMD units of X86 architecture. Experimental results demonstrate QCSR-SIMD achieves significant average speedup of 2.0 x compared to CSR-SIMD. © 2015, International Institute for General Systems Studies. All rights reserved.

Advances in Systems Science and Applications

SIMD acceleration of SpMV Kernel on multi-core CPU architecture

With the increase in the resolution of images, arises the need to compress these images effectively without much loss, for easy storage and transmission. Sparse matrices are matrices that have majority of their elements as zeroes, which brings in the possibility of storing just the non-zero elements in a space efficient manner using various formats. Images, which are essentially matrices, if somehow expressed as sparse matrices, can be similarly stored. The rectangular segmentation is a method that can be used to do so. In this paper, we analyze the space complexity of various storage formats for benchmark matrices and the suitability of these formats to compress images using rectangular segmentation method. © 2014 IEEE.

Department of Social Sciences

School of Social Sciences & Languages

2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)

Space complexity analysis of various sparse matrix storage formats used in rectangular segmentation image compression technique

In this paper we presented comparative analysis of sequential and parallel MPI application with dynamic instrumentation based Pin tool that can be used to assist in performance analysis of various parallel algorithms and computer software programs. We discussed various profiling and optimization tools apart from Pin and dynamic instrumentation techniques through which code can be analyzed, compared and monitored. A brief comparison of the cache analysis is also discussed with some considerations in order to highlight the approaches and technologies used by pin tool to achieve the optimum performance of an application.

2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN)

Program analysis with dynamic instrumentation Pin and performance tools

AES (Advanced Encryption Standard) is an effective encryption algorithm in applications like Internet to provide cyber security and also in smart cards. Multi-core and Field-Programmable Gate Arrays (FPGAs) are the promising solution for the performance up gradation. The main focus of this paper is to increase the throughput of the AES algorithm through hardware and software techniques. Various approaches for efficient hardware implementation of the AES algorithm is based on architectural optimization techniques like pipelining, loop unrolling and iterative design. Here we have adopted pipelining technique to increase the speed of the algorithm by processing multiple rounds simultaneously. Software parallelization techniques with OpenMP standard is used to increase the speedup of the algorithm compared to its sequential version. A pipelined architecture AES-128 core is implemented using Xilinx xc5vlx110t-1 device can achieve a throughput of 31.25Gbps which is more effective than previous ASIC implementations. By implementing the AES algorithm using OpenMP we achieve speed up of 1.08 in the dual core processor.