This paper presents comparative study on radio frequency (RF) stability performance of Double Gate MOSFET (DG-MOSFET) and Double Gate Tunnel FET (DG-TFET). A non-quasi static small signal model is used to extract small signal parameters which are then verified with extracted parameters through simulation. The high frequency performance of DG-MOSFET and DG-TFET is evaluated by extracting RF Figure of Merit (FoM) such as cut-off frequency (f t ), maximum oscillation frequency (f max ) along with stability factor. The result shows that DG-TFET has better cut-off frequency and stability performance as compared to DG-MOSFET.

Sivasankaran K

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Partha Sharathi Mallick

Department of Instrumentation

School of Electrical Engineering

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

A comparative study of radio frequency stability performance of Double Gate MOSFET and Double Gate Tunnel FET

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)

This article presents the bias and geometry optimization procedure for the radio frequency (RF) stability performance of nanoscale symmetric double-gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs). The stability model can provide hints for optimizing the DG-MOSFET under an RF range. The device parameters are extracted for different bias and geometry conditions through numerical simulation, and the RF figures of merit such as cut-off frequency (ft) and maximum oscillation frequency (fmax), along with stability factor, are calculated for an optimized structure. The proposed structure exhibits good RF stability performance.

Fulltext

Journal of Semiconductors

Stability performance of optimized symmetric DG-MOSFET

This article presents structure and bias optimization techniques for the radio frequency (RF) stability of silicon nanowire transistor. The RF parameters are extracted using device simulation. The device stability is obtained for various bias conditions and geometry, and observed that the proposed device structure shows good stability response. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2114–2117, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27016

Microwave and Optical Technology Letters

Bias and geometry optimization of silicon nanowire transistor: Radio frequency stability perspective

This paper presents radio frequency (RF) performance and high frequency stability of Double Gate Tunnel FET (DG TFET). A non-quasi static small signal model is used to extract small signal parameters which are then verified with extracted parameters through simulation. The high frequency performance of DG TFET is evaluated by extracting RF parameters like cut-off frequency (f t ), maximum oscillation frequency (f max ) and stability factor (K). The result shows that DG TFET has cut-off frequency of 350GHz and unconditionally stable from 11GHz onwards.

Journal	Data powered by Typeset2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)
Publisher	Data powered by TypesetIEEE
Open Access	No