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Open Access
Open AccessA low power and soft error resilience guard-gated Quatro based flip flop in 45nm CMOS technology
Published in IET Wiley
2021
DOI: 10.1049/cds2.12052
Pages: 1 - 10
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About the journal
| Journal | Data powered by TypesetIET circuit devices and systems |
|---|---|
| Publisher | Data powered by TypesetIET Wiley |
| Open Access | Yes |
Authors (1)
Satheesh Kumar S- ASIC implementation of high speed pipelined DDR SDRAM controller
- Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS
- A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module
- SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology
