This paper proposes a novel approach for reducing the shifting and capture power by a fan-out aware modified adjacent X-filling technique. This approach reduces the time complexity and number of iterations in addition to the reduction of test power. Experimental results obtained from ISCAS'89 circuits are compared with existing techniques prove that the proposed ATPG methodology is suitable to test the scan based system-on-chip architecture with reduced testing power.
|Journal||Data powered by Typeset2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies|
|Publisher||Data powered by TypesetIEEE|